View N04Q1618C2B_1864354.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

N04Q1618C2B stock no. 23451-d 11/06 1 the specification is adva nce information and subjec t to change without notice. advance information ami semiconductor, inc. ulp memory solutions 670 north mccarthy blvd. suite 220 milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 4mb ultra-low power asynchronous cmos sram w/ dual vcc and vccq for ultimate power reduction 256k16 bit power saver technology overview the n04q16yyc2b are ultra-low power memory devices containing a 4 mbit static random access memory organized as 262,144 words by 16 bits. the device is designed and fabricated using ami semiconductor?s advanced cmos technology to provide ultra-low active and standby power. the device operates with two chip enable (ce1 and ce2) controls and output enable (oe ) to allow for easy memory expansion. byte controls (ub and lb ) allow the upper and lower bytes to be accessed independently. the 4mb sram is optimized for the ultimate in low power and is suited for various applications where ultra-low- power is critical such as medical applications, battery backup and power sensitive hand-held devices. the unique page mode operation saves active operating power and the dual power supply rails allow very low voltage operation while maintaining 3v i/o capability. the device can operate over a very wide temperature range of 0 o c to +70 o c for the lowest power and is also available in the industrial range of -40 o c to +85 o c. the devices are available in standard bga and tsop packages. the devices are also available as known good die (kgd) for embedded package applications. features ? multiple power supply ranges 1.1v - 1.3v 1.65v - 1.95v ? dual vcc / vccq power supplies 1.2v vcc with 3v vccq 1.8v vcc with 3v vccq ? very low standby current 50na typical for 1.2v operation ? very low operating current 400a typical for 1.2v operation at 1s ? very low page mode operating current 80a typical for 1.2v operation at 1s ? simple memory control dual chip enables (ce1 and ce2) byte control for independent byte operation output enable (oe ) for memory expansion ? automatic power down to standby mode ? bga, tsop and kgd options ? rohs compliant product options part number typical standby current vcc (v) vccq (v) speed (ns) typical operating current operating temperature n04q1612c2bx-15c 1 50na 1.2 1.2, 1.8, 3.0 150ns 0.4 ma @ 1mhz 0 o c to +70 o c N04Q1618C2Bx-15c 1 50na 1.8 1.8, 3.0 150ns 0.4 ma @ 1mhz N04Q1618C2Bx-70c 200na 70ns 0.6 ma @ 1mhz N04Q1618C2Bx-85c 200na 85ns 0.6 ma @ 1mhz 1. part numbers are under development. please cont act your local sales representative for details.
stock no. 23451-d 11/06 2 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. pin configurations (4mb) pin descriptions pin name pin function a 0 -a 17 address inputs we write enable input ce1 chip enable 1 input ce2 chip enable 2 input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 7 lower byte data input/output i/o 8 -i/o 15 upper byte data input/output v cc core power v ccq power for i/o v ss core ground nc not connected pin one 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 4 a 3 a 2 a 1 a 0 ce1 i/o 0 i/o 1 i/o 2 i/o 3 vcc vss i/o 4 i/o 5 i/o 6 i/o 7 we a 16 a 15 a 14 a 13 a 12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 5 a 6 a 7 oe ub lb i/o 15 i/o 14 i/o 13 i/o 12 vss vccq i/o 11 i/o 10 i/o 9 i/o 8 ce2 a 8 a 9 a 10 a 11 a 17 tsop ii 123456 a lb oe a 0 a 1 a 2 ce2 b i/o 8 ub a 3 a 4 ce1 i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ss i/o 11 a 17 a 7 i/o 3 v cc e v ccq i/o 12 nc a 16 i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 nc a 12 a 13 we i/o 7 h nc a 8 a 9 a 10 a 11 nc 48 pin bga (top)
stock no. 23451-d 11/06 3 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. functional block diagram functional description ce1 ce2 we oe ub 1 lb 1 i/o 0 - i/o 15 1 1. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - i/o 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. mode power hxxxxx high z standby 2 2. when the device is in standby mode, control inputs (we , oe , ub , and lb ), address inputs and data input/outputs are internally isolated from any external in fluence and disabled from exerti ng any influence externally. standby xlxxxx high z standby 2 standby l h x x h h high z standby standby lhl x 3 3. when we is invoked, the oe input is internally disabled and has no effect on the circuit. l 1 l 1 data in write 3 active lhhl l 1 l 1 data out read active lhhh l 1 l 1 high z active active capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf address inputs (a1 - a4) address inputs (a0, a5 - a17) word address decode logic 4mb ram array word mux input/ output mux and buffers page address decode logic control logic ce1 ce2 we oe ub lb i/o0 - i/o7 i/o8 - i/o15
stock no. 23451-d 11/06 4 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions ab ove those indicated in the operating section of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 260 o c, 10sec o c operating characteristics (over specified temperature range, 0 o - 70 o c) item symbol device conditions min. typ max unit core supply voltage v cc n04q1612... 1.2v core device 1.1 1.2 1.3 v n04q1618... 1.8v core device 1.65 1.8 1.95 i/o supply voltage v ccq n04q1612... 1.2v core device 1.1 3.3 v n04q1618... 1.8v core device 1.65 3.3 input high voltage v ih 0.8 x vccq v cc +0.3 v input low voltage v il ?0.3 0.2 x vccq output high voltage v oh i oh = -100ua v cc ?0.2 v output low voltage v ol i ol = 100ua 0.2 v input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe = v ih or chip disabled 0.5 a
stock no. 23451-d 11/06 5 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. power consumption (t a = 0 o c - 70 o c) device pn speed typ 1 max n04q1612c2bx- 15c standby current 2 isb chip disabled v cc = 1.3v, v in = v cc or 0 50 500 na read/write current 3 icc chip enabled, i out = 0 v cc =1.3v, v in =v ih or v il 1us 0.4 0.5 ma 150ns 2 3 page mode current iccp chip enabled, i out = 0 v cc =1.3v, v in =v ih or v il 1us 80 100 a 150ns 300 450 N04Q1618C2Bx- 15c standby current isb chip disabled v cc = 1.9v, v in = v cc or 0v 50 500 na read/write current icc chip enabled, i out = 0 v cc =1.9v, v in =v ih or v il 1us 0.4 0.5 ma 150ns 2 3 page mode current iccp chip enabled, i out = 0 v cc =1.9v, v in =v ih or v il 1us 80 100 a 150ns 400 500 N04Q1618C2Bx- 70c/85c standby current isb chip disabled v cc = 1.9v, v in = v cc or 0 0.2 1.5 a read/write current icc chip enabled, i out = 0 v cc =1.9v, v in =v ih or v il 1us 0.6 0.9 ma 70ns 85ns 67 page mode current iccp chip enabled, i out = 0 v cc =1.9v, v in =v ih or v il 1us 0.1 0.2 ma 70ns 85ns 0.8 1 1. typical values are measured at vcc=vcc typ., t a =25c and not 100% tested. 2. this device assumes a standby m ode if the chip is disabled (ce1 high or ce2 low). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. this applies to all isb values. 3. this parameter is specified with the out puts disabled to avoid exter nal loading effects. the user must add current required t o drive output capacitance expected in the actual system . this applies to all icc and iccp values.
stock no. 23451-d 11/06 6 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. power savings with page mode operation (we = v ih ) note: page mode operation is a method of addressing the sram to save operating current. the internal organization of the sram is optimized to allow this unique operating mode to be used as a valuable power saving feature. the only thing that needs to be done is to address the sram in a manner that the internal page is left open and 16-bit words of data are read from the open page. by treating addresses a1 - a4 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power srams. page address (a0, a5-a17) lb , ub oe ce1 ce2 word address (a1-a4) open page word 1 word 2 word 16 ...
stock no. 23451-d 11/06 7 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 30pf operating temperature 0 to +70 o c timing item symbol -70 -85 -150 units min. max. min. max. min. max. read cycle time t rc 70 85 150 ns address access time t aa 70 85 150 ns page mode address access time t aap 70 85 150 ns chip enable to valid output t co 70 85 150 ns output enable to valid output t oe 35 45 75 ns byte select to valid output t be 70 85 150 ns chip enable to low-z output t lz 10 10 10 ns output enable to low-z output t olz 555ns byte select to low-z output t bz 10 10 10 ns chip disable to high-z output t hz 020020020ns output disable to high-z output t ohz 020020020ns byte select disable to high-z output t bhz 020020020 ns output hold from address change t oh 10 10 10 ns write cycle time t wc 70 85 150 ns chip enable to end of write t cw 50 60 120 ns address valid to end of write t aw 50 60 120 ns byte select to end of write t bw, 50 60 120 ns write pulse width t wp 40 50 100 ns address setup time t as 000ns write recovery time t wr 000ns write to high-z output t whz 20 20 20 ns data to write time overlap t dw 40 50 100 ns data hold from write time t dh 000 ns end write to low-z output t ow 555ns
stock no. 23451-d 11/06 8 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. timing of read cycle (ce1 = oe = v il , we = ce2 = v ih ) timing waveform of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid address lb , ub oe data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t be t blz ce1 ce2
stock no. 23451-d 11/06 9 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. timing waveform of page mode read cycle (we = v ih ) page address lb , ub oe t aa t co t hz t ohz t bhz t olz t oe high-z data out t be t blz ce1 ce2 word address t aap t rc
stock no. 23451-d 11/06 10 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. timing waveform of write cycle (we control) timing waveform of write cycle (ce1 control) address data in ce1 ce2 lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t bw address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t lz t dw t bw data out t whz ce1 (for ce2 control, use inverted signal)
stock no. 23451-d 11/06 11 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. 44-lead tsop ii package (t44) note: 1. all dimensions in inches (millimeters) 2. package dimensions exclude molding flash 18.410.13 10.160.13 see detail b 1.100.15 11.760.20 0.45 0.30 0.80mm ref detail b 0.80mm ref 0 o -8 o 0.20 0.00
stock no. 23451-d 11/06 12 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. ball grid array package dimensions (mm) de e = 0.75 ball matrix type sd se j k 60.10 80.10 0.375 0.375 1.125 1.375 full side view top view bottom view e d a1 ball pad corner (3) 1.240.10 0.280.05 0.15 0.05 z z 1. 0.350.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
stock no. 23451-d 11/06 13 the specification is adva nce information and subjec t to change without notice. N04Q1618C2B advance information ami semiconductor, inc. ordering information ? 2006 ami semiconductor, inc. all rights reserved. ami semiconductor, inc. ("amis") reserves the right to change or modify the information contained in this data sheet and the pr oducts described therein, without prior notice. amis does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. amis makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does amis assume an y liability arising out of t he application or use of any product or circuit described herein. amis does not authorize use of its products as critical components in any application in which the failure of the amis product may be expected to result in significant injury or death, incl uding life support systems and critical medical instruments. revision history revision date change description a october 2005 initial advanced release b february 2006 raised maximum vcc to 3.6v for 3v device added green packages changed dual rail to ?q? part designator c july 2006 seperated 1,8v dual rail and 3v single rail updated vccq for tsop d september 2006 converted to ami semiconductor n04q 16 xx c2b x - xx x 70 = 70ns 85 = 85ns 15 = 150ns (under development) t2 = 44-pin tsop ii green (rohs compliant) b2 = 48-ball bga green (rohs compliant) w = wafer (kgd) temperature package type performance c = 0 o c - 70 o c operating voltage 12 = 1.2v (under development) 18 = 1.8v q = low power sram with vccq for dual rail operation

▲Up To Search▲

Price & Availability of N04Q1618C2B

	To Download N04Q1618C2B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .